The present invention relates to semiconductor devices and their fabrication. More particularly, the invention relates to preparation of a silicon-on-insulator (“SOI”) substrate in which at least a portion of the SOI substrate is stressed.
Various methods exist for fabricating SOI substrates. In one particular example according to the prior art, illustrated in FIG. 1, an SOI substrate 10 is fabricated to contain a region of strained silicon 12 having tensile stress in which a transistor, for example, an n-type field effect transistor (“NFET”) will be formed. The tensile stressed silicon region 12 overlies a region 14 containing silicon germanium (SiGe) having relaxed stress, and the SiGe region, in turn, overlies a bulk silicon region 18, as separated therefrom by a buried oxide (“BOX”) layer 16 containing borophosphosilicate glass (“BPSG”).
To fabricate the prior art SOI substrate 10, a starting SOI substrate is provided which includes a compressive top SiGe layer which overlies the bulk silicon layer 18, separated therefrom by a BOX layer including BPSG. Thereafter, a layer of silicon 12 is grown epitaxially from the surface of the SiGe layer. After patterning the silicon layer 12 and SiGe layer 14, e.g., by etching in accordance with a photolithographically defined mask layer (not shown), the temperature of the SOI substrate is elevated to a point at which the BPSG BOX layer 16 becomes flowable. This then causes the BOX layer 16 to soften and “flow”. As a result, the stress in the SiGe layer 14 relaxes, and in consequence, a tensile stress develops in the silicon layer 12 above the SiGe layer 14.
One of the drawbacks of the prior art SOI substrate 10 is that after the active silicon region 12 is defined, the SiGe stressor layer 14 continues to underlie the active silicon region 12 in which the transistor is to be formed. This fact hinders some of the flexibility of the design of the transistor to be formed thereon, as the underlying SiGe layer 14 can contribute to junction capacitance, reducing the performance benefit to be gained from the SOI structure. In addition, the permanent presence of the SiGe layer 14 can lead to undesirable diffusion of germanium and arsenic into portions of the transistor to be formed in the active silicon region 12. Another drawback is that threading defects can occur which can lead to shorts of the gate dielectric.